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Computer Organization and Architecture

The Computer Organization and Architecture course and lab cover the entire field of computer design updated with the most recent research and innovations in computer structure and function. The lab is cloud-based, device-enabled, and can easily be integrated with an LMS. The computer architecture course and lab also provides knowledge on the areas such as I/O functions and structures, RISC, and parallel processors with real-world examples enhancing the text for reader interest.
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  • Delivery method: eLearning
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Outline

Lessons 1:
Introduction

  • What’s New in the Eleventh Edition
  • Support of ACM/IEEE Computer Science and Computer Engineering Curricula
  • Objectives
  • Example Systems
  • Plan of the Text

Lessons 2:
Basic Concepts and Computer Evolution

  • Organization and Architecture
  • Structure and Function
  • The IAS Computer
  • Gates, Memory Cells, Chips, and Multichip Modules
  • The Evolution of the Intel x86 Architecture
  • Embedded Systems
  • ARM Architecture

Lessons 3:
Performance Concepts

  • Designing for Performance
  • Multicore, Mics, and GPGPUs
  • Two Laws that Provide Insight: Amdahl’s Law and Little’s Law
  • Basic Measures of Computer Performance
  • Calculating the Mean
  • Benchmarks and Spec

Lessons 4:
A Top-Level View of Computer Function and Interconnection

  • Computer Components
  • Computer Function
  • Interconnection Structures
  • Bus Interconnection
  • Point-to-Point Interconnect
  • PCI Express

Lessons 5:
The Memory Hierarchy: Locality and Performance

  • Principle of Locality
  • Characteristics of Memory Systems
  • The Memory Hierarchy
  • Performance Modeling Of A Multilevel Memory Hierarchy

Lessons 6:
Cache Memory

  • Cache Memory Principles
  • Elements of Cache Design
  • Intel x86 Cache Organization
  • The IBM z13 Cache Organization
  • Cache Performance Models

Lessons 7:
Internal Memory

  • Semiconductor Main Memory
  • Error Correction
  • DDR DRAM
  • eDRAM
  • Flash Memory
  • Newer Nonvolatile Solid-State Memory Technologies

Lessons 8:
External Memory

  • Magnetic Disk
  • RAID
  • Solid State Drives
  • Optical Memory
  • Magnetic Tape

Lessons 9:
Input/Output

  • External Devices
  • I/O Modules
  • Programmed I/O
  • Interrupt-Driven I/O
  • Direct Memory Access
  • Direct Cache Access
  • I/O Channels and Processors
  • External Interconnection Standards
  • IBM z13 I/O Structure

Lessons 10:
Operating System Support

  • Operating System Overview
  • Scheduling
  • Memory Management
  • Intel x86 Memory Management
  • ARM Memory Management

Lessons 11:
Number Systems

  • The Decimal System
  • Positional Number Systems
  • The Binary System
  • Converting Between Binary and Decimal
  • Hexadecimal Notation

Lessons 12:
Computer Arithmetic

  • The Arithmetic and Logic Unit
  • Integer Representation
  • Integer Arithmetic
  • Floating-Point Representation
  • Floating-Point Arithmetic

Lessons 13:
Digital Logic

  • Boolean Algebra
  • Gates
  • Combinational Circuits
  • Sequential Circuits
  • Programmable Logic Devices

Lessons 14:
Instruction Sets: Characteristics and Functions

  • Machine Instruction Characteristics
  • Types of Operands
  • Intel x86 and ARM Data Types
  • Types of Operations
  • Intel x86 and ARM Operation Types
  • Appendix 13A Little-, Big-, and Bi-Endian

Lessons 15:
Instruction Sets: Addressing Modes and Formats

  • Addressing Modes
  • x86 and ARM Addressing Modes
  • Instruction Formats
  • x86 and ARM Instruction Formats

Lessons 16:
Assembly Language and Related Topics

  • Assembly Language Concepts
  • Motivation For Assembly Language Programming
  • Assembly Language Elements
  • EXAMPLES
  • Types of assemblers
  • Assemblers
  • Loading and Linking

Lessons 17:
Processor Structure and Function

  • Processor Organization
  • Register Organization
  • Instruction Cycle
  • Instruction Pipelining
  • Processor Organization for Pipelining
  • The x86 Processor Family
  • The ARM Processor

Lessons 18:
Reduced Instruction Set Computers

  • Instruction Execution Characteristics
  • The Use of a Large Register File
  • Compiler-Based Register Optimization
  • Reduced Instruction Set Architecture
  • RISC Pipelining
  • MIPS R4000
  • SPARC
  • Processor Organization For Pipelining
  • CISC, RISC, And Contemporary Systems

Lessons 19:
Instruction-Level Parallelism and Superscalar Processors

  • Overview
  • Design Issues
  • Intel Core Microarchitecture
  • ARM Cortex-A8
  • ARM Cortex-M3

Lessons 20:
Control Unit Operation and Microprogrammed Control

  • Micro-Operations
  • Control of the Processor
  • Hardwired Implementation
  • Microprogrammed Control

Lessons 21:
Parallel Processing

  • Multiple Processor Organizations
  • Symmetric Multiprocessors
  • Cache Coherence and the MESI Protocol
  • Multithreading and Chip Multiprocessors
  • Clusters
  • Nonuniform Memory Access

Lessons 22:
Multicore Computers

  • Hardware Performance Issues
  • Software Performance Issues
  • Multicore Organization
  • Heterogeneous Multicore Organization
  • INTEL Core i7-5960X
  • ARM Cortex-A15 MPCore
  • IBM z13 Mainframe

Appendix A: System Buses

  • A.1 Bus Structure
  • A.2 Multiple-Bus Hierarchies
  • A.3 Elements of Bus Design

Appendix B: Victim Cache Strategies

  • B.1 Victim Cache
  • B.2 Selective Victim Cache

Appendix C: Interleaved Memory

Appendix D: The International Reference Alphabet

Appendix E: Stacks

  • E.1 Stacks
  • E.2 Stack Implementation
  • E.3 Expression Evaluation

Appendix F: Recursive Procedures

  • F.1 Recursion
  • F.2 Activation Tree Representation
  • F.3 Stack Implementation
  • F.4 Recursion And Iteration

Appendix G: Additional Instruction Pipeline Topics

  • G.1 Pipeline Reservation Tables
  • G.2 Reorder Buffers
  • G.3 Tomasulo’s Algorithm
  • G.4 Scoreboarding